📝 Knowledge Test: Real-Time Clocks

Real-Time Clocks Knowledge Test

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This page contains 12 interactive knowledge checks on the DS3231 lab. The questions cover why a separate clock chip is needed, the BCD time registers, the control and status registers, alarms and the latched INT/SQW interrupt, wiring that interrupt to a GPIO, and the Linux kernel driver.

Please remember that many of the quizzes have multiple correct answers, and you must select all applicable options to succeed. I have balanced the lengths of the answers, so take your time to evaluate each option.

Good luck!

Derek.

Part 1: Timekeeping and the time registers

Quiz

Select 0/2

Which of the following statements about keeping time on an embedded system are correct?

derekmolloy.ie

A 32.768 kHz crystal is used because 32 768 is 2¹⁵, so a chain of fifteen divide-by-two stages produces exactly 1 Hz.

The DS3231 holds ±2 ppm because it is trimmed once at the factory, at 25 °C, and then relies on the crystal's own stability.

A tuning-fork watch crystal runs slower as its temperature moves away from about 25 °C, whichever direction it moves in.

A 20 ppm crystal error is too small to matter, because it adds up to only about 20 microseconds of drift each day.

Quiz

Select 0/1

The DS3231's hours register (0x02) reads 0x69. What time does it hold?

derekmolloy.ie

9 PM, in 12-hour mode: bit 6 selects 12-hour mode and bit 5 is PM.

Hour 69 in 24-hour mode, which is out of range, so the time is invalid.

Hour 29 in 24-hour mode, which is out of range, so the time is invalid.

9 AM, in 12-hour mode: bit 6 selects 12-hour mode and bit 5 is AM.

Concept Match

Match the DS3231 bit to what it does

derekmolloy.ie

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

OSF (0x0F, bit 7)

drag a definition here…

INTCN (0x0E, bit 2)

drag a definition here…

Century (0x05, bit 7)

drag a definition here…

A1M1 (0x07, bit 7)

drag a definition here…

BBSQW (0x0E, bit 6)

drag a definition here…

Definition Pool

When set, alarm 1 ignores the seconds field.

Flips when the year register rolls over from 99 to 00.

Set whenever the oscillator has stopped; the time cannot be trusted until software clears it.

Keeps the INT/SQW pin working while the chip runs on its coin cell.

Chooses whether the INT/SQW pin signals alarms or outputs a square wave.

Quiz

Select 0/2

Why should a program read the seven time registers in one I2C transaction (a pointer write, a repeated START, then a 7-byte read)?

derekmolloy.ie

The DS3231 copies the time into a buffer at each START, so one transaction returns bytes from a single instant.

The DS3231 only answers a read of seven bytes, and it refuses any shorter read with a NACK.

Reading registers one at a time stops the oscillator briefly, and that sets the OSF flag.

Separate reads can straddle a tick, so the seconds, minutes and hours may come from different moments.

Part 2: Control, status and alarms

Quiz

Select 0/1

A freshly powered module's status register (0x0F) reads 0x88. Which statement is correct?

derekmolloy.ie

BSY and OSF are set: a temperature conversion is running and it stopped the oscillator.

A1F and A2F are set: both alarms went off while the module sat in its packaging.

OSF and EN32kHz are set: the time is a default value, and the 32 kHz output is on.

EOSC and BBSQW are set: the oscillator stays stopped until both bits are cleared.

Quiz

Select 0/1

Alarm 1's registers (0x07 to 0x0A) hold 0x30, 0x80, 0x80, 0x80, and A1IE and INTCN are both set. When does INT/SQW go low?

derekmolloy.ie

Never, because setting the mask bit in the day/date register disables alarm 1.

Once a minute, when the seconds reach 30, because the other three fields are masked.

Every second, because three of the four fields are masked and so always match.

At 30 minutes past every hour, because 0x30 is the value of the minutes field.

Quiz

Select 0/2

Alarm 1 has fired and INT/SQW is low. Which of the following statements are correct?

derekmolloy.ie

INT/SQW stays low until software writes a 0 to A1F in the status register.

The DS3231 releases INT/SQW by itself after one second, like a short pulse.

Writing a 1 to A1F is how software acknowledges the alarm and clears it.

An edge-triggered GPIO will miss every later alarm if A1F is never cleared.

Code Cloze

C++

Complete the ESP32-S3 alarm handling (Zephyr, raw registers)

derekmolloy.ie

Drag snippets from the pool into the blanks so the program produces the output shown, then click Submit.

1#define REG_STATUS 0x0F /* DS3231 status register */

2#define STAT_OSF BIT(7) /* oscillator stopped */

3#define STAT_A2F BIT(1) /* alarm 2 fired */

4#define STAT_A1F BIT(0) /* alarm 1 fired */

6/* rtc_read() and rtc_write() are I2C helpers; rtc_int is the INT/SQW pin */

7static void alarm_work_handler(struct k_work *work);

8static K_WORK_DEFINE(alarm_work, alarm_work_handler);

10static void int_isr(const struct device *port, struct gpio_callback *cb,

11 gpio_port_pins_t pins)

12{

13 ·····(&alarm_work); /* no I2C in interrupt context */

14}

16static void alarm_work_handler(struct k_work *work)

17{

18 uint8_t st;

20 rtc_read(REG_STATUS, &st, 1);

21 st &= ~(····· | STAT_A2F); /* writing 0 clears the flag */

22 rtc_write(REG_STATUS, &st, 1);

23}

25/* INT/SQW is active low in the devicetree */

26gpio_pin_interrupt_configure_dt(&rtc_int, ·····);

Available Snippets

STAT_A1F

GPIO_INT_EDGE_TO_ACTIVE

GPIO_INT_LEVEL_HIGH

i2c_write

k_work_submit

STAT_OSF

GPIO_INT_EDGE_RISING

k_sleep

Part 3: Wiring and the Linux driver

Quiz

Select 0/2

INT/SQW is an open-drain output. Which of the following statements are correct?

derekmolloy.ie

A pull-up is only needed on the Raspberry Pi, because ESP32-S3 inputs are never left floating.

The DS3231 can pull the line low but never drives it high, so it needs a pull-up to read high.

Open drain means the pin is disconnected until an alarm has been enabled with A1IE or A2IE.

Without a pull-up, a released line floats, and the GPIO can see edges that are not alarms.

Q10

Concept Match

Match the Linux command or result to its meaning

derekmolloy.ie

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

UU at 0x68 in i2cdetect -y 1

drag a definition here…

sudo hwclock -w

drag a definition here…

sudo hwclock -s

drag a definition here…

echo 0 | sudo tee /sys/class/rtc/rtc0/wakealarm

drag a definition here…

Definition Pool

A kernel driver has claimed the address, so i2c-tools need -f to touch it.

Copies the Pi's system time into the RTC; the driver also clears OSF.

Sets the Pi's system time from the RTC, for example at boot without a network.

Disables the alarm and clears the alarm flags, which releases INT/SQW.

Q11

Code Order

Bring up the DS3231 on a Raspberry Pi

derekmolloy.ie

Drag the tiles to arrange the code in the correct order, then click Submit. Indentation is dynamically applied based on the location of braces.

sudo hwclock -w # after the UU check: set the RTC from the Pi's clock

sudo hwclock -r # read it back through /dev/rtc0

i2cdetect -y 1 # 0x68 now shows UU

i2cdetect -y 1 # 0x57 (EEPROM) and 0x68 (RTC) answer

sudo dtoverlay i2c-rtc ds3231 # load the kernel driver

Q12

Quiz

Select 0/1

The driver is loaded on a freshly powered module, and sudo hwclock -r reports 'ioctl(RTC_RD_TIME) to /dev/rtc0 to read the time failed: Invalid argument'. Why?

derekmolloy.ie

The coin cell is flat, so the chip cannot answer on the I2C bus and the read fails.

The registers hold BCD values, which the kernel's RTC core cannot convert to binary.

hwclock was run without -f, so the kernel blocked its access to address 0x68.

The driver sees OSF set and refuses to return a time that it knows has been lost.