Demo 6.1: Latches

Every circuit in this module so far has had one property in common, and it is worth naming before it stops being true. Give the circuit a set of inputs, wait long enough, and the outputs are determined. The same inputs always produce the same outputs. An adder given 5 and 3 produces 8 today and it produced 8 yesterday, and there is nothing else to know.

This demonstration breaks that, on purpose, with two gates.

The circuit here has a stretch of behaviour where the outputs are not a function of the inputs at all. Two different circuits with identical inputs can sit there showing different answers, and both of them are correct. What separates them is what happened earlier, and a circuit whose present depends on its past is a circuit that remembers.

The awkward first five minutes

There is a specific difficulty in meeting a latch for the first time, and it is worth being told about in advance rather than falling into it.

Look at the cross-coupled pair with both inputs idle and try to work out the outputs. The top gate needs to know what the bottom gate is producing. The bottom gate needs to know what the top gate is producing. Neither has an answer and there is no way in, and a student who assumes they have missed something will spend a long time looking for it.

Nothing has been missed. The question genuinely has no answer from that starting point. So the demonstration opens exactly there, with both outputs drawn as dashed lines with question marks in them, and it will not resolve them until you give it somewhere to start. That is not a limitation of the drawing; it is the definition of the thing being drawn.

The way in is a property of the NOR gate you have known since the first week. A NOR gate with a 1 on any input produces 0, and it does so without needing to know anything about its other input. So assert Set or Reset, and one gate in the loop can be worked out on its own. Once that one is settled the other has both its inputs, and the whole loop unrolls from there in three steps.

How to use it

The SR latch starts unknown and stays that way until you assert an input. Then use Step to walk the resolution one gate at a time. Do this properly at least once, then release the input and watch it hold. The Forget the state button puts it back to unknown so you can start again from a different direction. The toggle at the top switches between the NOR version, whose inputs are active high, and the NAND version, whose inputs are active low.

Gated SR latch is the same two NOR gates with two AND gates in front, so the latch only listens while the enable is high.

The D latch is the gated latch with an inverter, which removes the input combination that is not allowed. It also carries a timing diagram whose D and enable traces you can draw yourself by clicking on them.

Latches: SR, Gated SR and D

Two gates arguing with each other, and why that counts as remembering something.

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Two gates, each listening to the other.

Every circuit so far has had its outputs determined by its inputs.
This one does not, and the drawing opens saying so: both outputs are unknown and no amount of staring will produce them.
Assert Set or Reset and the loop can be unpicked one gate at a time.

Inputs, asserted high

Nothing can be worked out from here

Both inputs are idle, so neither NOR gate is being forced from outside. Each one needs the other's output before it can produce its own, and neither has one yet. This is not a gap in the drawing: the outputs of this circuit are not a function of its inputs, which is exactly what makes it different from everything before it. Assert S or R to give it somewhere to start.

S	R	Q	Q	what it does
0	0	no change	no change	holds whatever it had
0	1	0	1	clears Q to 0
1	0	1	0	sets Q to 1
1	1	0	0	not allowed: both outputs the same

Active high and active low

Both versions are the same idea with a different gate.
The NOR latch is asserted by putting a 1 on an input and sits idle at 0, so its inputs are active high.
The NAND latch is asserted by putting a 0 on an input and sits idle at 1, so its inputs are active low, and their names are written S and R to say so.
A bar over a name means the pin does its job when it is low.

Watch the inputs change sides

Switch between the two and notice which pin arrives at the gate that produces Q.
In the NOR version it is R, because asserting Reset forces that gate to 0 and 0 is what Q should become.
In the NAND version it is S, because asserting Set forces that gate to 1.
The wiring has to change because the polarity did, and this is one of the most common ways to get a data sheet wrong.

Walkthrough

Step 1: Sit with the unknown state

Open the first tab and read the drawing before touching anything. Both inputs are at 0, both outputs are dashed, and both terminals show a question mark.

Try to work out Q. You cannot, and you should satisfy yourself about why rather than taking it on trust: each gate is waiting for the other one. This is the first circuit in the module where wait long enough and read the answer does not work.

Step 2: Force one gate, then follow the rest

Assert Set and press Step three times, reading what each step says.

Step 1 is the important one. The gate with Set on its input produces 0 because it is a NOR gate with a 1 on an input, and that conclusion needs no information about the feedback conductor at all. That is the foothold. Notice that only one output stops being dashed.

Step 2 is ordinary combinational work. The other gate now has one input from outside and one arriving on the feedback conductor, both known, so its output follows.

Step 3 is the one people skip. Take the second gate’s answer, feed it back into the first gate, and work the first gate out again. It gives the same value it gave before. That is what stable means for a loop, and without checking it you have not shown the circuit will stay where you put it.

Step 3: Take the input away

Return Set to 0 and watch what does not happen.

Both inputs are now idle, exactly as they were in Step 1, and yet the outputs are no longer unknown. Nothing is forcing either gate from outside any more. The top gate is producing what it produces because of what the bottom gate is feeding it, and the bottom gate is producing what it produces because of what the top gate is feeding it. Each is the other’s reason.

That circular argument is the memory. It is not a metaphor for storage and it is not a component that stores something; it is two gates that have agreed on a story and will keep telling it until something interrupts them. Assert Reset and watch the story change, then release it and watch the new one persist.

Step 4: Ask for both at once

Assert Set and Reset together.

Both gates are now forced from outside independently, and neither needs the feedback at all. Both outputs go to 0. Nothing breaks and nothing is damaged, and the circuit is perfectly stable.

The trouble is what the outputs now mean. The second output is supposed to be the complement of the first, and it is not, so the labels have stopped being true. Anything downstream reading both of them is reading nonsense. That is why this combination is ruled out: not because it hurts the part but because you asked the part for two contradictory things and got an answer that cannot be interpreted.

Worse is what happens on the way out. Release both inputs at the same instant and the latch has to fall one way or the other, and which way depends on which of the two gates happens to be a little faster than the other on that particular day. That is not something you can design around. You will see it for yourself when you build one of these in the laboratory, and different benches will not agree.

Step 5: The same circuit with the polarity turned over

Switch to the NAND version.

It is the same topology with the gate changed. Where the NOR latch is asserted by putting a 1 on an input and idles at 0, the NAND latch is asserted by putting a 0 and idles at 1. Its inputs are active low, and the bars over the names are there to say so: a bar means the pin does its job when it is low.

Now look at which input arrives at the gate that produces Q. In the NOR version it is Reset, because asserting Reset forces that gate to 0 and 0 is what Q should become. In the NAND version it is Set, because asserting Set forces that gate to 1. The wiring had to change because the polarity did.

Active low is not a curiosity. Most of the parts you will meet use it for at least some of their pins, for the electrical reason met in the decoder demonstration, and mistaking an active-low pin for an active-high one is one of the most common ways to misread a data sheet. Get used to the bar.

Step 6: Add a way of not listening

Open Gated SR latch. Set S to 1 with the enable at 0 and watch nothing at all happen.

The mechanism is worth stating precisely, because it is not what students usually assume. Disabling the latch does not switch anything off or disconnect anything. With the enable at 0 both AND gates produce 0, and 0 on both inputs of an SR latch is the hold case. So disabling the latch feeds it the one input combination that means leave things exactly as they are.

Now raise the enable and watch the pending S take effect immediately. Lower it again and change S and R as much as you like; nothing gets through.

What has not been fixed is the disallowed combination. S and R both high with the enable high still arrives at the latch as both inputs asserted, and it is still not allowed. The enable controls when the latch listens, not what it is being told.

Step 7: Design the fault out

Open The D latch.

The gated latch has a combination that must never be applied, which means every designer who uses one has to remember a rule, and rules that are only in people’s heads eventually get broken. The D latch removes the possibility instead. One input, called D, goes to Set directly and to Reset through an inverter, so the two can never be asserted together because one of them is always the complement of the other.

This is worth recognising as a general move. Given a part with a combination that must be avoided, you can write the rule in the documentation and hope, or you can wire the part so the combination cannot occur. The second is always better, and it usually costs one gate.

Step 8: Read it over time

The timing diagram on that tab shows the same latch with time running left to right, and the shaded stretches are where the enable is high.

Look at what Q does inside a shaded stretch. It copies D exactly, following every change D makes for as long as the enable stays high, as though the latch were not in the circuit at all. That is what transparent means. When the enable returns to 0, Q keeps whatever D happened to be at that moment and stops paying attention.

Click on the D and enable traces to draw your own. Two things are worth trying deliberately. Make D change several times inside one long enable stretch, and watch Q wobble along with it: anything reading Q during that window sees the wobble, and a store that changes while you are reading it is not much of a store. Then make the enable high for one slot only and see that the wobble disappears.

Notice also that Q is drawn as unknown until the first time the enable goes high. Until then the latch has never been told anything, which is the same point the first tab opened on.

Check your understanding

Quiz

Select 0/1

A NOR-based SR latch has both inputs at 0 and you are asked what Q is. What is the correct answer?

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Quiz

Select 0/1

Working out the state of a cross-coupled NOR pair has to start somewhere. What makes it possible to begin?

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Concept Match

Match each situation to what the latch does

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Quiz

Select 0/1

A gated SR latch has its enable at 0. Why do S and R have no effect?

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Quiz

Select 0/1

Why does a D latch have no combination of inputs that is disallowed?

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Wrap-up

Five things to take from this.

A latch has a set of inputs for which the outputs are not determined. That is not a defect, it is the point, and it is what separates this half of the subject from everything before it.
Two gates in a loop are worked out by finding the one that its own input forces, settling that one, then following the loop round, then checking that going round again changes nothing.
Holding is not a mode the circuit switches into. It is what is left when nothing is forcing either gate and each one is being kept in place by the other.
Both inputs asserted is stable but uninterpretable, and how it resolves when you release it is a matter of which gate happens to be faster. Take a note of this for the laboratory.
Active low is a wiring convention with a bar over the name, and turning the polarity over changes which pin goes where in the drawing.

The D latch solved one of the two problems with an SR latch. It cannot be asked for anything contradictory, and it stores a bit.

What it has not solved is the one the timing diagram makes obvious. While the enable is high the latch is transparent, and the value it holds keeps moving for as long as it is listening. If the rest of the system reads that output during the same period, it reads whatever the input happened to be doing at that instant rather than a settled stored value, and the circuit that is writing the latch and the circuit that is reading it end up interfering with each other.

The fix is not a different kind of memory. It is a way of controlling far more tightly when the latch is allowed to listen, and that is the subject of the next demonstration.