1.5 Processor families: ESP32, Arm Cortex-M, and Arm Cortex-A

To write efficient C++ and Rust code across our two-tier architecture, you need to understand what sits inside the silicon package on each board. A connected embedded system is rarely built around a standalone CPU chip; instead, it uses a System-on-Chip (SoC) that integrates one or more processor cores, SRAM, ROM, direct memory access (DMA) controllers, cryptographic accelerators, peripheral bus controllers (I²C, SPI, UART, CAN, USB, PCIe), and, on microcontroller leaf nodes, complete 2.4 GHz radio transceivers on a single die.

Instruction Set Architectures (ISAs) at the edge

Three Instruction Set Architectures dominate modern connected embedded systems:

1. Arm: Licensed as semiconductor intellectual property (IP) cores to hundreds of silicon vendors (including Broadcom, STMicroelectronics, Nordic Semiconductor, NXP, and Texas Instruments). Since the introduction of the ARMv7 and ARMv8/v9 architectures, Arm splits its processor families into three distinct profiles¹.
   • Cortex-A (Application profile): 32-bit and 64-bit (AArch64) processors with hardware Memory Management Units (MMUs), superscalar pipelines (out-of-order on the Cortex-A72 and A76, in-order on the A53), multi-level caches, and SIMD vector units (NEON), designed to run full operating systems such as Embedded Linux (e.g., Cortex-A53, Cortex-A72, Cortex-A76).
   • Cortex-R (Real-Time profile): High-clock-rate processors with tightly coupled memories (TCM) and deterministic interrupt response (often with dual-core lockstep for functional safety), used in automotive braking, storage controllers, and heterogeneous SoCs (e.g., Cortex-R5F).
   • Cortex-M (Microcontroller profile): Compact, deterministic 32-bit cores using the Thumb-2 instruction set, with a built-in Nested Vectored Interrupt Controller (NVIC), optional Memory Protection Unit (MPU), and low, predictable memory latency (tightly coupled or zero-wait SRAM; flash usually needs wait states or an accelerator above a few tens of MHz), designed for bare-metal or RTOS firmware (e.g., Cortex-M0+, M4F, M7, M33, M55).
2. Tensilica Xtensa: A configurable, extensible 32-bit RISC processor architecture (originally developed by Tensilica, now part of Cadence Design Systems) that allows chip designers to add custom instructions and DSP extensions. Xtensa LX6 and LX7 cores power the original Espressif ESP32 and the ESP32-S2/S3 series².
3. RISC-V: An open-standard, royalty-free Instruction Set Architecture originally developed at UC Berkeley (2010)³ and governed by RISC-V International. Because RISC-V is modular (built around a small base integer ISA (RV32I or RV64I) plus standard extensions for multiplication (M), atomics (A), single/double floating-point (F/D), compressed 16-bit instructions (C), and vector processing (V)), silicon vendors can implement custom cores without paying per-chip ISA royalties. Espressif’s newer C, H and P series (for example the ESP32-C3, C6, H2 and P4) use 32-bit RISC-V cores, while the ESP32-S3 remains Xtensa².

Tier 1 silicon: the ESP32 family and Arm Cortex-M leaf nodes

In this book, our primary Tier 1 microcontroller target is the Espressif ESP32 family, complemented in several interactive simulators by the Nordic Semiconductor nRF52840 (an Arm Cortex-M4F SoC).

The Espressif ESP32 evolution: from Xtensa LX6 to RISC-V

When Espressif released the ESP8266 (2014, Wi-Fi only) and the original ESP32 (2016, Wi-Fi and Bluetooth)², they transformed the economics of connected leaf nodes by offering complete wireless microcontroller modules with integrated antenna and flash for a few euro. Since then, the ESP32 line has expanded into specialised sub-families tailored to specific radio and compute workloads:

SoC Variant	CPU Core & ISA	Clock & SRAM	Wireless Radios	Key Embedded & AI Features
ESP32 (Original)	Dual-core 32-bit Xtensa LX6	160/240 MHz, 520 KB SRAM	Wi-Fi 4 (802.11b/g/n), BT 4.2 (Classic + BLE)	Two 12-bit SAR ADCs (18 ch), two 8-bit DACs, TWAI (CAN 2.0), 4 SPI, 2 I²C, 3 UART, hardware AES/SHA/RSA.
ESP32-S3	Dual-core 32-bit Xtensa LX7 + Ultra-Low-Power (ULP) co-processor	240 MHz, 512 KB SRAM (+ up to 8–16 MB Octal PSRAM)	Wi-Fi 4 (802.11b/g/n), BLE 5.0	PIE vector instructions for TinyML neural network and DSP acceleration; native USB OTG & USB-Serial/JTAG; TWAI (CAN).
ESP32-C3	Single-core 32-bit RISC-V (RV32IMC)	160 MHz, 400 KB SRAM	Wi-Fi 4 (802.11b/g/n), BLE 5.0	Pin- and cost-optimised replacement for legacy ESP8266 nodes; hardware secure boot and flash encryption.
ESP32-C6	High-performance 32-bit RISC-V (RV32IMAC) + LP RISC-V core	160 MHz (HP) / 20 MHz (LP), 512 KB SRAM	Wi-Fi 6 (802.11ax), BLE 5.3, IEEE 802.15.4 (Thread / Zigbee)	Multi-radio leaf node: supports Wi-Fi 6 Target Wake Time (TWT) for sleepy Wi-Fi nodes plus native 802.15.4 mesh networking and TWAI (CAN).
ESP32-H2	Single-core 32-bit RISC-V	96 MHz, 320 KB SRAM	BLE 5.3 + IEEE 802.15.4 (Thread 1.4 / Zigbee 3.0)	Dedicated ultra-low-power mesh and Matter-over-Thread leaf node (omits high-current Wi-Fi radio).

Hardware quirks to watch on the ESP32

Real embedded hardware always has silicon constraints that datasheets bury in footnotes. On the ESP32 family, keep two hardware rules in mind when designing circuits in Part II:

1. 3.3 V logic only: Every ESP32 and Raspberry Pi GPIO pin is strictly 3.3 V and not 5 V tolerant. Connecting a 5 V logic signal directly to a pin will permanently damage the SoC.
2. ADC2 and the Wi-Fi radio: On the ESP32 and ESP32-S3, the second SAR analogue-to-digital converter block (ADC2) shares internal hardware arbiters with the Wi-Fi transceiver. Once the Wi-Fi driver is active, reads on ADC2 pins fail or block. Always wire analogue sensors that must be read during wireless operation to ADC1 pins (Chapter 7).

Because Zephyr RTOS supports both the Xtensa (LX6/LX7) and 32-bit RISC-V instruction sets through its Devicetree and Kconfig abstraction layer (Section 1.3), the C++ and C application code you write in this book compiles across the ESP32, ESP32-S3, and ESP32-C6, as well as Arm Cortex-M boards such as the Nordic nRF52840 (64 MHz Cortex-M4F, 256 KB SRAM, 1 MB Flash, BLE 5 + IEEE 802.15.4), by changing the target board name passed to west build -b <board>, with board-specific overlays where peripherals differ (there is no Wi-Fi on the nRF52840, for example, and no 802.15.4 radio on the ESP32 or ESP32-S3).

Tier 2 silicon: Raspberry Pi and heterogeneous gateway SoCs

On the gateway tier, our primary platform is the Raspberry Pi (running 64-bit Raspberry Pi OS), compared alongside industrial and heterogeneous alternatives from Kunbus (Revolution Pi) and the BeagleBoard.org Foundation (BeagleBone Black and BeagleY-AI).

The Raspberry Pi progression: from ARMv6 to the Pi 5 and RP1 southbridge

When the Raspberry Pi Foundation launched the original Model B in 2012 for $35, its goal was to encourage school students to study computer science. Because it provided a mainline-capable Linux environment, a 40-pin 3.3 V expansion header (from the Model B+ onward) exposing 26 GPIOs, I²C, SPI, UART, and PWM, and stable long-term availability, industry rapidly adopted the Raspberry Pi as an embedded gateway platform.

Across its generations, the Raspberry Pi family has scaled its Arm processor architecture by more than an order of magnitude:

Model	SoC & CPU Architecture	Clock & RAM	Power & Storage	I/O, Networking & Architecture Notes
Pi 1 (B/B+) & Pi Zero	Broadcom BCM2835: single-core ARM1176JZF-S (32-bit ARMv6)	700 MHz – 1 GHz, 256–512 MB	5 V ~1.1 A micro-USB; microSD	Pi 1 B+ introduced the standard 40-pin GPIO header and HAT EEPROM spec; USB and 10/100 Ethernet shared a single USB 2.0 root port via an SMSC LAN9514 hub.
Pi 3 Model B+ & Zero 2 W	Broadcom BCM2837B0 / RP3A0: quad-core Arm Cortex-A53 (64-bit ARMv8-A)	1.0 – 1.4 GHz, 512 MB – 1 GB LPDDR2	5 V ~2.5 A micro-USB; microSD	First 64-bit Raspberry Pi generation; dual-band 802.11ac Wi-Fi (3 B+) or 2.4 GHz 802.11n (Zero 2 W), and BLE 4.2.
Raspberry Pi 4 Model B	Broadcom BCM2711 (28 nm): quad-core Arm Cortex-A72 (64-bit ARMv8-A, out-of-order)	1.5 – 1.8 GHz, 1, 2, 4, or 8 GB LPDDR4	5 V 3 A (15 W) USB-C; microSD	Dedicated RGMII Gigabit Ethernet (removed from USB bottleneck); 2× USB 3.0 + 2× USB 2.0 via PCIe; dual micro-HDMI 4K; VideoCore VI GPU.
Raspberry Pi 5	Broadcom BCM2712 (16 nm): quad-core Arm Cortex-A76 (64-bit ARMv8.2-A, crypto extensions)	2.4 GHz, 2, 4, 8, or 16 GB LPDDR4X	5 V 5 A (27 W USB-C PD); microSD or PCIe NVMe	Roughly 2–3× the CPU throughput of Pi 4; RP1 I/O southbridge4 over PCIe; external PCIe 2.0/3.0 x1 FFC connector; onboard battery-backed RTC and power button; VideoCore VII GPU (Vulkan 1.2).

Figure 1.9

Raspberry Pi 4 and Pi 5 I/O architecture

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Click any block or link to see what it does.

BothPi 4Pi 5

All blocksGPIO path

Raspberry Pi 4

BCM2711 SoC4× Cortex-A72

On-die peripherals40-pin headerGPIO, I²C, SPI, UART, PWMPCIe x1VL805 USB 3.02× USB 3.0 + 2× USB 2.0RGMIIGigabit Ethernet PHY

Raspberry Pi 5

BCM2712 SoC4× Cortex-A76 @ 2.4 GHzPCIe 2.0 x4RP1I/O southbridge

40-pin headerGPIO, I²C, SPI, UART, PIO

USB2× USB 3.0 + 2× USB 2.0

Gigabit Ethernet

External PCIe x1

NVMe SSD or AI HAT+Hailo NPU

Select a block or a link, or switch on the GPIO path.

Figure 1.9. Architectural comparison between the Raspberry Pi 4 and the Raspberry Pi 5. On the Pi 4, the 40-pin header peripherals live directly inside the BCM2711 SoC. On the Pi 5, low-speed and medium-speed I/O is moved off the main 16 nm processor die onto the custom RP1 southbridge connected over a 4-lane PCIe bus⁴.

Why the Pi 5 RP1 southbridge breaks legacy GPIO code

Notice the structural change in Figure 1.9. On the Raspberry Pi 1 through 4, the GPIO registers resided on the main Broadcom SoC bus, and older user-space libraries such as wiringPi and pigpio bypassed the Linux kernel to mmap() physical SoC memory directly via /dev/mem or /dev/gpiomem. On the Raspberry Pi 5, the 40-pin GPIO header is driven by the external RP1 southbridge over PCIe, with a completely different register layout⁴. Libraries that hardcode BCM2835/BCM2711 register offsets fail on a Pi 5 unless they are rewritten for it (pigpio has not been; wiringPi 3.x has). By contrast, code written against the modern Linux kernel GPIO character device (/dev/gpiochip*) using libgpiod v2 (Chapter 6) and Devicetree overlays (Chapter 4) moves between the Pi 4, Pi 5, and other Linux boards with little change, provided it finds the chip and line by name rather than by number (the Pi 5 header moved from gpiochip4 to gpiochip0 with kernel 6.6.45).

Industrial Compute Modules and the Revolution Pi

A standard Raspberry Pi 4 or 5 with a microSD card and consumer HDMI/USB connectors is built for development benches and light commercial use, not for a high-vibration 24 V industrial control cabinet. For industrial production, Raspberry Pi offers the Compute Module 4 (CM4) and Compute Module 5 (CM5) ($30–$80 in volume): compact System-on-Module (SoM) boards that place the BCM2711 or BCM2712 SoC, LPDDR4 (CM4) or LPDDR4X (CM5) RAM, and soldered eMMC flash (up to 32 GB on CM4 and 64 GB on CM5, eliminating microSD mechanical contact failure) onto two 100-pin high-density board-to-board connectors.

A classic industrial example built around the Compute Module is the Kunbus Revolution Pi (RevPi Connect 5): an open-source, DIN-rail-mounted industrial PC powered from 24 V DC that wraps a CM5 in an EN 61131-2 compliant enclosure with galvanic isolation, dual Ethernet ports, RS-485, CAN FD, hardware watchdogs, and a PREEMPT_RT real-time patched Raspberry Pi OS image.

Heterogeneous multi-core SoCs: BeagleBone PRUs and BeagleY-AI

While a two-board split (an ESP32 connected to a Raspberry Pi over wireless or a bus) is the clearest way to learn the two-tier architecture, many industrial System-on-Chips combine both tiers on the exact same piece of silicon. This architecture is called Asymmetric Multiprocessing (AMP) (explored in Chapter 12):

• BeagleBone Black and the Octavo OSD335x SiP: Powered by the Texas Instruments Sitara AM335x (1 GHz Arm Cortex-A8), the BeagleBone Black (and its single-package Octavo OSD335x System-in-Package derivative) includes two Programmable Real-Time Units (PRUs) on the same die⁵. The PRUs are deterministic 200 MHz 32-bit RISC cores (not Arm cores) with zero-instruction-cache jitter and single-cycle (5 ns) access to dedicated I/O pins, communicating with the Linux Cortex-A8 core through shared SRAM and the kernel remoteproc / RPMsg framework.
• BeagleY-AI (TI AM67A): Represents the modern generation of heterogeneous AIoT gateway silicon in a Raspberry Pi form factor. Its Texas Instruments AM67A SoC integrates three distinct compute engines on a single chip:
  1. Application cores: Quad-core 64-bit Arm Cortex-A53 (1.4 GHz) running Embedded Linux.
  2. Real-time microcontroller core: A dedicated Arm Cortex-R5F core (800 MHz, runnable with Zephyr RTOS) for low-latency deterministic control and safety monitoring.
  3. Edge AI accelerators: Dual C7x DSPs paired with Matrix Multiply Accelerators (MMA) delivering 4 TOPS (tera-operations per second) of deep-learning inference without taxing the Linux CPU cores.

Similarly, on the Raspberry Pi 5, the external PCIe 2.0/3.0 lane allows you to attach the Raspberry Pi AI HAT+, which adds a Hailo-8L (13 TOPS) or Hailo-8 (26 TOPS) neural processing unit directly to the gateway’s PCIe bus (Chapter 21).

As Chen et al. (AI+HW 2035, 2026)⁶ emphasise, this shift toward heterogeneous, domain-specific silicon, where general-purpose Linux application cores, deterministic RTOS control cores, and memory-centric neural accelerators share high-speed on-chip or PCIe interconnects, is how connected embedded systems overcome the energy and memory walls over the coming decade.

🧩 Knowledge Check

Concept Match

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A program written with the pigpio library works on a Raspberry Pi 4 but fails on a Raspberry Pi 5. Why?

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The BeagleY-AI runs Linux on its Cortex-A53 cores and Zephyr on its Cortex-R5F core. What is this arrangement called?

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What do you need to change to rebuild a Zephyr application written for an ESP32-S3 so that it runs on an nRF52840?

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Footnotes

1. Arm Limited, Arm Architecture Reference Manual for A-Profile (AArch64) and Armv7-M / Armv8-M Architecture Reference Manuals, Cambridge, UK, https://developer.arm.com/documentation. ↩

2. Espressif Systems, ESP32, ESP32-S3, and ESP32-C6 Technical Reference Manuals, https://www.espressif.com/en/support/documents/technical-documents. ↩ ↩² ↩³

3. A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, The RISC-V Instruction Set Manual, Volume I: User-Level ISA, EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-54, May 2014 (governed by RISC-V International, https://riscv.org/). ↩

4. Raspberry Pi Ltd, Raspberry Pi RP1 Peripherals Datasheet and BCM2711 ARM Peripherals Datasheet, https://datasheets.raspberrypi.com/. ↩ ↩² ↩³

5. D. Molloy, Exploring BeagleBone: Tools and Techniques for Building with Embedded Linux, 2nd ed., Wiley, 2019; and Exploring Raspberry Pi: Interfacing to the Real World with Embedded Linux, Wiley, 2016. ↩

6. Y. Chen, J. Cong, A. Mirhoseini, C. Kozyrakis, S. Mitra, Y. LeCun, R. Puri, et al., AI+HW 2035: Shaping the Next Decade, 2026. ↩