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This page contains 10 interactive knowledge checks covering the material in Chapter 1: the Information Value Loop, sensor suitability and multisensory interactions, the IoT/IIoT/Physical AI landscape, the two-tier edge architecture, the Internet of Collaborating Things (IoCT), processor families, connectivity trade-offs, and Lab 1.
Please remember that many of the quizzes have multiple correct answers, and you must select all applicable options to succeed. I have balanced the lengths of the answers, so take your time to evaluate each option carefully.
Good luck.
Derek.
Part 1: Sensing, value loops, and physical constraints
A neuromorphic event camera clocks out full-frame pixel arrays at a fixed 30 Hz rate, increasing data volume in exchange for higher spatial resolution.
A sensor that consistently reads 52.0%, 52.1%, and 52.0% when the true moisture is 50.0% has high repeatability, and its +2.0% systematic bias can be removed by calibration.
Fusing an accelerometer (which measures gravity but suffers from vibration) with a gyroscope (which tracks fast rotation but drifts over time) is an example of multisensory synergy.
Active sensors such as 60 GHz mmWave radar draw less power than passive thermistors because they only receive ambient electromagnetic radiation from the room.
Q3
Quiz
Select 0/2
In 'AI+HW 2035: Shaping the Next Decade' (Chen et al., 2026), what is meant by the 'memory wall' (and communication wall), and how does it shape connected embedded design?
Overcoming the memory and energy walls requires cross-layer co-design across hardware technologies, compact physics-informed algorithms, and edge applications.
The energy spent moving data across off-chip memory buses and wireless network links now exceeds the energy spent performing arithmetic computations on that data.
Microcontroller flash memory wears out after a few hundred read cycles, requiring all sensor buffers to be streamed directly to cloud DRAM before processing.
Because cloud GPUs have unlimited memory bandwidth, edge nodes should avoid local filtering and transmit raw high-rate ADC waveforms over Wi-Fi.
Part 2: IIoT, Physical AI, and the two-tier architecture
Which of the following statements accurately reflect findings from the WEF Industrial Internet (2015), WEF MINDS (2026), and WEF Next-Generation Physical Autonomy (2026) reports?
Unlike digital AI systems that process static tokens, Physical AI systems must manage continuous mechanical forces, predict motion, and maintain safe operation even when network connectivity drops.
Across the 2025/2026 WEF MINDS cohort, organisations reported that data quality and technical infrastructure limitations are completely solved by public cloud LLMs without edge hardware.
Interconnected domestic safety alarms such as the Nest Protect rely exclusively on a home's 5 GHz Wi-Fi router to communicate with each other during a fire.
In the 'outcome economy' phase of the Industrial Internet, companies shift from selling physical hardware to selling quantifiable, guaranteed operational results measured by field sensors.
Q5
Quiz
Select 0/3
Why does our two-tier edge architecture place Zephyr RTOS on the ESP32 leaf node and Embedded Linux on the Raspberry Pi gateway, rather than running Linux on both?
Standard Linux user-space processes suffer from scheduling and virtual-memory jitter that can delay microsecond bit-banging or high-rate closed-loop control.
A Raspberry Pi 4 or 5 draws several watts of power and takes 10 to 25 seconds to boot, whereas an ESP32 running Zephyr boots in milliseconds and can sleep at tens of microamps on a battery.
Mainline Linux requires a hardware Memory Management Unit (MMU) and tens of megabytes to gigabytes of DRAM, whereas an ESP32 executes in a single physical address space with a few hundred kilobytes of SRAM.
Zephyr RTOS and Embedded Linux share zero configuration concepts, so engineers must use completely incompatible hardware description formats on the two tiers.
Part 3: The Internet of Collaborating Things (IoCT) and edge silicon
In the Internet of Collaborating Things (IoCT) architecture proposed by Hanafy et al. (2026), how do visiting and resident devices collaborate securely across administrative domains?
Instead of funnelling all data vertically through distant cloud servers, co-located devices collaborate horizontally by pooling local sensing, compute, and actuation resources.
Every sensor sample must pass through a Large Language Model in the control plane before a motor actuator is allowed to update its PWM duty cycle.
An agentic control plane handles discovery, hardware attestation, and peer negotiation out-of-band, issuing short-lived signed capability tokens that data-plane brokers enforce at wire speed.
The IoCT data plane executes portable compute 'nanotasks' (for example, in attested WebAssembly/TEE sandboxes) and accesses hardware 'nanoservices' exposed by nearby devices.
Q7
Concept Match
Match the processor or SoC to its architectural profile
In Europe, the 868 MHz ISM band used by LoRaWAN is completely unregulated, allowing a sensor node to transmit continuously at 100% duty cycle at any power level.
CAN bus uses differential signalling on a twisted pair and non-destructive bitwise arbitration, allowing the highest-priority frame (lowest ID) to win the bus without collision delay.
The IEEE 802.15.4 standard defines only the PHY and MAC layers (with a 127-byte maximum frame); multi-hop mesh routing is provided by upper layers such as Zigbee or Thread (6LoWPAN/IPv6).
CoAP runs over UDP with a compact 4-byte header and supports RESTful methods and resource discovery, making it well suited to sleepy 802.15.4 mesh nodes.
Q9
Quiz
Select 0/3
When designing an ESP32 sensor circuit or wiring a Raspberry Pi 4/5 GPIO header, which electrical and hardware rules must you obey?
Both the Raspberry Pi 40-pin header and ESP32 GPIO pins operate at 3.3 V logic levels and are not 5 V tolerant; applying 5 V directly will damage the SoC.
On the ESP32 and ESP32-S3, the ADC2 peripheral shares hardware with the Wi-Fi radio, so analogue sensors read while Wi-Fi is active should be wired to ADC1.
The Raspberry Pi 4 and Raspberry Pi 5 include eight built-in 12-bit analogue-to-digital converter pins on the 40-pin header, so no external ADC chip is required.
I2C uses open-drain lines (SDA and SCL) that require pull-up resistors to 3.3 V so the bus returns cleanly to a logic high state.
Q10
Quiz
Select 0/3
In Lab 1, you imaged Raspberry Pi OS, connected headless over SSH, and controlled the onboard ACT LED via /sys/class/leds/ACT/. Which of the following statements are true of a modern Raspberry Pi OS (Bookworm/Trixie) setup?
The historical default 'pi' user and 'raspberry' password were removed in April 2022; user credentials, SSH keys, and NetworkManager Wi-Fi settings are pre-configured in Raspberry Pi Imager.
Writing 'timer' to /sys/class/leds/ACT/trigger causes the kernel LED class driver to expose delay_on and delay_off attributes for configuring the blink period in milliseconds.
Unplugging the 5 V USB-C power cord at any time is completely safe on Embedded Linux because the ext4 root filesystem never caches writes in RAM.
A Raspberry Pi 4 has no onboard battery-backed RTC, so if it boots without network access to an NTP server its system clock will not know the current wall-clock time.
